Full five-day course: Nanometer CMOS ICs


*** This course starts 8.30 and ends about 18.00 (sometimes even 18.30). It includes exercises during day/evening and a final examination, to be made at home. The results must be sent-in two weeks after the course. When sufficient, the participants will get an official diploma.

*** This course is meant as a comprehensive tutorial on state-of-the-art CMOS ICs for engineers working in the different disciplines of the semiconductor research and industry: design, modeling, technology development, CAD development, test development, product engineering, failure analysis, reliability engineering, packaging, etc.



Contents

Basic principles.
MOS physics. Characteristics. Equations. Capacitances.
Geometry effects.
Temperature behaviour. Short- and narrow-channel effects. Mobility reduction
Subthreshold behaviour and leakage current mechanisms.
CMOS technology.
Extensive lithography overview. Basic CMOS processing steps. Process flow. From a basic nMOS process to a 22nm CMOS process. Future processes, SOI, Finfet
CMOS design.
Extensive discussion on electrical, logic and layout design, with 50nm CMOS design rules and process cross sections
CMOS memories.
Memory architectures, SRAM, DRAM, ROM, PROM, E(E)PROM, NAND- and NOR-flash memories, stand-alone and embedded memories.
VLSI and ASICs.
Design flow, hierarchy levels. IP cores. re-use. ASICs. ASIC design styles: standard cell, gate array (sea-of-gates) designs, PLDs, (re)configurable logic, embedded FPGAs, etc.
Low-power.
Battery overview. Extensive discussion and complete overview of existing technology and design options for low power and low leakage.
Robustness of ICs.
Extensive discussion of reliability and signal integrity issues: latch-up, punch-through, ESD protection circuits, hot-carrier degradation. Electromigration, NBTI, joule heating, clocking, timing, signal integrity, supply and substrate noise, power integrity, decoupling, cross-talk, noise margins, EMC, soft-errors and variability, etc.
Testing, debugging, failure analysis and yield, packaging
Complete overview of Testing, Shmoo-plots, design for debug, basics of yield and simple model, packaging characteristics and trends, diagnosis techniques, state-of-the-art failure analysis techniques. Repair, focussed ion beam, etc.
Scaling trends, roadblocks and "What's next?"
Costs and roadblocks for 15nm technologies and beyond. Speed and power trends. Design, masks and processing costs. Roadblocks and solutions. End of Moore's Law! More than Moore: sensors, actuators, MEMS, biological, biomedical apps.

The course includes a copy of the book: "Nanometer CMOS ICs, from Basics to ASICs" Springer 2013 (update) and a copy of the book: "Bits on Chips" 2011